// INT16CXX.H:  saving and restoring registers during interrupt



#if defined _16C61 || defined _16C71 || defined _16C84 || defined INT_min_style

 // CODE : Up to 2048 words (PCLATH not used)
 // RAM :  Located in bank 0 and mapped to bank 1, RP1 is unused

 #define  int_save_registers \
    char svrWREG, svrSTATUS; \
    svrWREG = W; \
    svrSTATUS = swap(STATUS);

 #define  int_restore_registers \
    STATUS = swap(svrSTATUS); \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG);

#endif


#if defined _16C64  ||  defined _16C622  ||  defined INT_med_style

 // CODE : Up to 2048 words (PCLATH not used)
 // RAM :  Located in bank 0 and 1 (no mapping), RP1 is unused

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma char svrWREG = 0x20 \
   #pragma char svrWREGmirror = 0xA0 \
   #pragma rambank 0 \
    char svrSTATUS; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = 0; \
   #pragma update_RP 1 \
    svrSTATUS = W;

 #define  int_restore_registers \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#if defined _16C65 || defined _16C73 || defined _16C74 || defined INT_max_style

 // CODE : Above 2048 words (PCLATH is saved)
 // RAM :  Located in bank 0 and 1 (no mapping between bank 0 and 1)

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma char svrWREG = 0x20 \
   #pragma char svrWREGmirror = 0xA0 \
   #pragma rambank 0 \
    char svrSTATUS, svrPCLATH; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = 0; \
   #pragma update_RP 1 \
    svrSTATUS = W; \
    svrPCLATH = PCLATH; \
    PCLATH = 0;

 #define  int_restore_registers \
    PCLATH = svrPCLATH; \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#if defined _16C620  ||  defined _16C621  ||  defined INT_bank0_style

 // CODE : Up to 2048 words (PCLATH not used)
 // RAM :  Located in bank 0 only (no mapping either), RP1 is unused

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma rambank 0 \
    char svrWREG, svrSTATUS; \
    bit RP0_save; \
   #pragma update_RP 0 \
    if (RP0)  { \
        RP0 = 0; \
        RP0_save = 1; \
    } \
    else \
        RP0_save = 0; \
   #pragma update_RP 1 \
    svrWREG = W; \
    svrSTATUS = swap(STATUS);

 #define  int_restore_registers \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
    if (RP0_save) \
        RP0 = 1; \
   #pragma update_RP 1 \

#endif


#ifdef INT_com_style

 // CODE : Up to 2048 words (PCLATH not used)
 // RAM :  Located in 2 banks, some locations are mapped, RP1 is unused

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma rambank - \
    char svrWREG; \
   #pragma rambank INT_rambank \
    char svrSTATUS; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = INT_rambank % 2; \
   #pragma update_RP 1 \
    svrSTATUS = W;

 #define  int_restore_registers \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#ifdef INT_lgen_style

 // CODE : Up to 2048 words (PCLATH not used)
 // RAM :  Both RP0 and RP1 are active, some RAM locations are mapped

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma rambank - \
    char svrWREG; \
   #pragma rambank INT_rambank \
    char svrSTATUS; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = INT_rambank % 2; \
    RP1 = INT_rambank / 2; \
   #pragma update_RP 1 \
    svrSTATUS = W;

 #define  int_restore_registers \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#ifdef INT_midgen_style

 // CODE : Above 2048 words (PCLATH is saved)
 // RAM :  Located in 2 banks, some locations are mapped, RP1 is unused

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma rambank - \
    char svrWREG; \
   #pragma rambank INT_rambank \
    char svrSTATUS, svrPCLATH; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = INT_rambank % 2; \
   #pragma update_RP 1 \
    svrSTATUS = W; \
    svrPCLATH = PCLATH; \
    PCLATH = 0;

 #define  int_restore_registers \
    PCLATH = svrPCLATH; \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#ifdef INT_gen_style

 // CODE : Above 2048 words (PCLATH is saved)
 // RAM :  Both RP0 and RP1 are active, some RAM locations are mapped

 #ifdef int_save_registers
  #error Multiple INT_xxx_style (the chip header file defines the correct one)
 #endif

 #define  int_save_registers \
   #pragma rambank - \
    char svrWREG; \
   #pragma rambank INT_rambank \
    char svrSTATUS, svrPCLATH; \
   #pragma update_RP 0 \
    svrWREG = W; \
    W = swap(STATUS); \
    RP0 = INT_rambank % 2; \
    RP1 = INT_rambank / 2; \
   #pragma update_RP 1 \
    svrSTATUS = W; \
    svrPCLATH = PCLATH; \
    PCLATH = 0;

 #define  int_restore_registers \
    PCLATH = svrPCLATH; \
    W = swap(svrSTATUS); \
   #pragma update_RP 0 \
    STATUS = W; \
    svrWREG = swap(svrWREG); \
    W = swap(svrWREG); \
   #pragma update_RP 1 \

#endif


#ifndef int_save_registers
 // an undefined chip type
 #error Interrupt save and restore macro's are undefined for this chip
 // The interrupt save type is normally defined in the chip header file
#endif